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Proceedings Paper

Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance
Author(s): Michael Orshansky; Linda Milor; Michael Brodsky; Ly Nguyen; Gene Hill; Yeng-Kaung Peng; Chenming Hu
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Paper Abstract

Statistical characterization of gate CD variability of a production CMOS process reveals a large spatial intra-field component, strongly dependent on the local layout patterns. We present a novel measurement based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design. A rigorous analysis of the impact of intra-field variability on circuit performance is undertaken. We show that intra-field CD variation has a significant detrimental effect on the overall circuit performance by reducing the average speed by up to 20 percent. We derive a model quantitatively relating intra- field CD variance delay degradation. We propose a mask-level spatial gate CD correction algorithm to reduce the intra- field and overall variability, resulting in circuit performance improvement, and provide an analytical model to evaluate the effectiveness of correction for variance reduction.

Paper Details

Date Published: 5 July 2000
PDF: 10 pages
Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389050
Show Author Affiliations
Michael Orshansky, Univ. of California/Berkeley (United States)
Linda Milor, Advanced Micro Devices, Inc. (United States)
Michael Brodsky, Univ. of California/Berkeley (United States)
Ly Nguyen, Univ. of California/Berkeley (United States)
Gene Hill, Advanced Micro Devices, Inc. (United States)
Yeng-Kaung Peng, Advanced Micro Devices, Inc. (United States)
Chenming Hu, Univ. of California/Berkeley (United States)


Published in SPIE Proceedings Vol. 4000:
Optical Microlithography XIII
Christopher J. Progler, Editor(s)

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