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Proceedings Paper

Impact of MEEF on low k1 lithography and mask inspection
Author(s): Qi-De Qian
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Paper Abstract

In this paper, we present a comparative simulation study of mask defect impact in a high MEEF process and its detectability under a mask inspection too. A simulation mode for a mask inspection system is constructed and validated by comparing the simulated signal with data collected from an inspection tool. With this calibrated mode, defect images and scan signals from programmed defect pattens are studied. The corresponding wafer CD variations caused by programmed defects are simulated using a photolithography simulator. We find that for a mask defect of a given size, its impact on wafer varies greatly from location to location, depending on the MEEF of the host patterns surrounding the defect. In comparison, the signal from a high-resolution inspection tool varies linearly with defect size and is nearly independent of the host patterns. Once the MEEF starts its sharp increase, the sensitivity of the inspection tool is required to increase at the same rate. An inspection tool operating at its resolution limit generally could not follow the sharp increase in MEEF once the wafer process starts to degrade. It is therefore important to control the MEEF in the original pattern design to ensure that residual defect does not cause circuit malfunction. Extra margins may have to be introduced in the design rule to account for the impact of residual defects.

Paper Details

Date Published: 5 July 2000
PDF: 6 pages
Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389048
Show Author Affiliations
Qi-De Qian, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 4000:
Optical Microlithography XIII
Christopher J. Progler, Editor(s)

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