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Proceedings Paper

64x64 smart pixel array for deformable membrane devices
Author(s): Kris Seunarine; Ian Underwood; Stephen C. Graham; David G. Vass; M. I. Newsam; J. Tom M. Stevenson; Alan M. Gundlach; R. J. Woodburn
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Paper Abstract

In this paper we describe the development of a CMOS VLSI backplane for use with micromachined silicon nitride membrane mirrors. The backplane consists of an array of 4096 pixels which are addressed by a 6-bit row decoder. Data enters the chip as a 64-bit logic word at standard CMOS 0-5V levels and is converted to 0-50V at the pixel level by an optimized cascade voltage switch logic circuit.

Paper Details

Date Published: 21 June 2000
PDF: 10 pages
Proc. SPIE 3990, Smart Structures and Materials 2000: Smart Electronics and MEMS, (21 June 2000); doi: 10.1117/12.388908
Show Author Affiliations
Kris Seunarine, Univ. of Edinburgh (United Kingdom)
Ian Underwood, Univ. of Edinburgh (United Kingdom)
Stephen C. Graham, Univ. of Edinburgh (United Kingdom)
David G. Vass, Univ. of Edinburgh (United Kingdom)
M. I. Newsam, Univ. of Edinburgh (United Kingdom)
J. Tom M. Stevenson, Univ. of Edinburgh (United Kingdom)
Alan M. Gundlach, Univ. of Edinburgh (United Kingdom)
R. J. Woodburn, Univ. of Edinburgh (United Kingdom)

Published in SPIE Proceedings Vol. 3990:
Smart Structures and Materials 2000: Smart Electronics and MEMS
Vijay K. Varadan, Editor(s)

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