Share Email Print

Proceedings Paper

Resist thickness optimization for multiple resists in a research and development lithography environment
Author(s): David Ashby Steele; Branden Linley; Tien Dinh
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

As production critical dimensions shrink from 0.25 micrometer generations down to 0.18 micrometer and farther, the demands of process control often have to be judged alongside throughput concerns. The resulting balance between these concerns is the result of a multitude of factors. In a lithography environment that produces multiple variants upon a similar device, one approach toward keeping resist processing uniformity down to manageable levels is to limit processing on a given track-stepper photocell to a single layer, with multiple variants upon only a few resist processes. If enough photo-cluster cells are present, this is a workable scheme. However, in the event that multiple devices are being produced out of a lithography environment with demanding resist capacity needs, inventive measures need to be taken in order to keep a manageable balance between throughput and process variation. More specifically, in the event that multiple resist processes are being managed within a single photo-cluster cell, resist process non-uniformity issues may arise due to the conflicting needs of the different resists. Therefore, due to the needs of multiple resist process support within a single photo-cell, any singular process may not be fully optimized. At AMD's Sub-micron Development Center (SDC) in Sunnyvale, California, a series of experiments were run with the intention of achieving the most optimized groups of I-line or DUV resist for a given resist thickness. Thickness output variables, such as range and thickness uniformity, were evaluated with respect to varying degrees of resist temperature within a single coater cup environment. From the initial results, further adjustments from the optimized resist temperature were performed in order to achieve a singular resist temperature for the entire resist block. In this paper, the limitations of track processing, specifically resist temperature control within a single resist coat cup environment, will be highlighted. Analyzed contour data generated by the Tencor/Prometrix FT750 will demonstrate the relationship between mean thickness, thickness uniformity and resist temperature changes, and how best to identify an optimized resist thickness for both single wafer and wafer to wafer processing. Lastly, from the output data collected, the best processing practice and placement of resists within a single coat cup environment can then be extended across an entire set of I-line and DUV photo-cells, leading to the optimization of several resists across a multiple track environment.

Paper Details

Date Published: 23 June 2000
PDF: 12 pages
Proc. SPIE 3999, Advances in Resist Technology and Processing XVII, (23 June 2000); doi: 10.1117/12.388363
Show Author Affiliations
David Ashby Steele, Advanced Micro Devices, Inc. (United States)
Branden Linley, Advanced Micro Devices, Inc. (United States)
Tien Dinh, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3999:
Advances in Resist Technology and Processing XVII
Francis M. Houlihan, Editor(s)

© SPIE. Terms of Use
Back to Top