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Proceedings Paper

Effects of process parameters on pattern-edge roughness of chemically amplified resists
Author(s): Hui Peng Koh; Qunying Lin; Xiao Hu; Lap Hung Chan
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Paper Abstract

Line-edge roughness (LER) has been identified to cause variation in critical dimension that affects the fidelity of pattern transfer and results in greater variation in device electrical performance. In present study, the effects of aerial image quality and resist processing parameters on the severity of LER are studied. Two chemically amplified resists (CARs) with both acetal and ESCAP-type protection groups are tested and compared. It is found that the image-log-slope (ILS) at pattern edge and the resist contrast are the two major factors affecting the magnitude of LER. The ILS is alterable by pattern density, pattern width, defocus conditions and the application of PSM. On the other hand, the shape and slope of the contrast curve are dependent on both soft bake and post-exposure bake temperature. Due to the finite contrast of resist, solubility change occurs across some dose interval. This corresponds to a boundary width at the aerial image that dictates the transition zone across the pattern edge. As the boundary width region is associated with higher roughness film, smaller boundary width could be translated to better LER. Nevertheless, a three-step development model is used to explain the dependence of LER on pattern density. Basically the discrepancy is due to differential progress of the development front at different ILS when developing time is fixed. In addition, changing the shape and slope of the resist contrast curve through different processing routes could directly modify the boundary width and therefore the LER. The attributes causing different LER performances of the two resists are also discussed.

Paper Details

Date Published: 23 June 2000
PDF: 12 pages
Proc. SPIE 3999, Advances in Resist Technology and Processing XVII, (23 June 2000); doi: 10.1117/12.388308
Show Author Affiliations
Hui Peng Koh, Nanyang Technological Univ. (Singapore)
Qunying Lin, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Xiao Hu, Nanyang Technological Univ. (Singapore)
Lap Hung Chan, Chartered Semiconductor Manufacturing Ltd. (Singapore)

Published in SPIE Proceedings Vol. 3999:
Advances in Resist Technology and Processing XVII
Francis M. Houlihan, Editor(s)

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