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Proceedings Paper

Fast search block-matching motion estimation algorithm using FPGA
Author(s): Vera Ying Y. Chung; Man To Wong; Neil W. Bergmann
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Paper Abstract

Many fast search block-matching motion estimation (BMME) algorithms have been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a new regular fast search block-matching motion estimation algorithm named Two Step Search (2SS). The 2SS BMME will then be implemented by 8 Xilinx XC6216 fine-grain, sea-of-gate FPGA chips. The experimental and simulation results shows that it can have better algorithmic performance and can be implemented by FPGA chips very cost-effectively for video compression applications. Also, the 30 frames per second real time 2SS BMME video compression can be obtained by using eight Xilinx XC6216 FPGAs.

Paper Details

Date Published: 30 May 2000
PDF: 9 pages
Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); doi: 10.1117/12.386693
Show Author Affiliations
Vera Ying Y. Chung, La Trobe Univ. (Australia)
Man To Wong, Univ. of New South Wales (Australia)
Neil W. Bergmann, Queensland Univ. of Technology (Australia)


Published in SPIE Proceedings Vol. 4067:
Visual Communications and Image Processing 2000
King N. Ngan; Thomas Sikora; Ming-Ting Sun, Editor(s)

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