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Proceedings Paper

Coprocessor architecture for MPEG-4 video object rendering
Author(s): Christoph Heer; Carolina Miro; Anne Lafage; Mladen Berekovic; Giovanni Ghigo; Thorsten Selinger; Kai-Immo Wels
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Paper Abstract

The most crucial backend algorithm of the new MPEG-4 standard is the computational expensive rendering of arbitrary shaped video objects to the final video scene. This co-processor architecture presents a solution for the scene rendering of the CCIR 601 video format with an arbitrary number of video objects. For the very high data bandwidth rate a hierarchical memory concept has been implemented. The total size of all rendered objects for one scene may reach two times the size of the CCIR 601 format. Running at 100 MHz clock frequency, the co-processor achieves a peak performance at about two billion multiply- accumulate operations. The co-processor has been designed for a 0.35 micrometers CMOS technology. About 60% of the overall area of 52 mm2 is used for on-chip static memory. The power consumption of the co-processor has been estimated with 1 W.

Paper Details

Date Published: 30 May 2000
PDF: 8 pages
Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); doi: 10.1117/12.386563
Show Author Affiliations
Christoph Heer, Infineon Technologies AG (Germany)
Carolina Miro, Ecole Nationale Superieure des Telecommunications (France)
Anne Lafage, Ecole Nationale Superieure des Telecommunications (France)
Mladen Berekovic, Univ. Hannover (Germany)
Giovanni Ghigo, Ctr. Studi e Laboratori Telecomunicazioni (Italy)
Thorsten Selinger, Heinrich-Hertz-Institut fuer Nachrichtentechnik Berlin GmbH (Germany)
Kai-Immo Wels, Heinrich-Hertz-Institut fuer Nachrichtentechnik Berlin GmbH (Germany)


Published in SPIE Proceedings Vol. 4067:
Visual Communications and Image Processing 2000
King N. Ngan; Thomas Sikora; Ming-Ting Sun, Editor(s)

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