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Proceedings Paper

VLSI architecture for motion estimation on a single-chip video camera
Author(s): Alexander Roach; Alireza Moini
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Paper Abstract

This paper presents a flexible architecture for motion estimation and compensation using a 1D pipelined systolic array. It has been specifically designed to implement the four-step search algorithm but can easily be adapted to a wide range of other reduced-complexity search algorithms. The intention is for the architecture to be incorporated into the digital compression unit of a single-chip video camera, the target application of which is as a device enabling people to communicate using sign-language over a standard phone line. The complete architecture has been implemented as register transfer level VHDL code and its functionality has been verified by simulation. The final VLSI layout will be a combination of synthesized and custom- designed cells.

Paper Details

Date Published: 30 May 2000
PDF: 10 pages
Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); doi: 10.1117/12.386562
Show Author Affiliations
Alexander Roach, Univ. of Adelaide (Australia)
Alireza Moini, Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 4067:
Visual Communications and Image Processing 2000
King N. Ngan; Thomas Sikora; Ming-Ting Sun, Editor(s)

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