Share Email Print
cover

Proceedings Paper

Accelerated yield learning in agressive lithography
Author(s): Kevin M. Monahan; Scott M. Ashkenaz; Xing Chen; Patrick J. Lord; Mark Andrew Merrill; Rich Quattrini; James N. Wiley
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As exposure wavelengths decrease from 248 nm to 193, 157, and even 13 nm (EUV), small process defects can cause collapse of the lithographic process window near the limits of resolution, particularly for the gate and contact structures in high- performance devices. Such sensitivity poses a challenge for lithography process module control. In this work, we show that yield loss can be caused by a combination of macro, micro, CD, and overlay defects. A defect is defined as any yield- affecting process variation. Each defect, regardless of cause, is assumed to have a specific 'kill potential.' The accuracy of the lithographic yield model can be improved by identifying those defects with the highest kill potential or, more importantly, those that pose the highest economic risk. Such economic considerations have led us to develop a simple heuristic model for understanding sampling strategies in defect metrology and for linking metrology capability to yield and profitability.

Paper Details

Date Published: 2 June 2000
PDF: 12 pages
Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); doi: 10.1117/12.386505
Show Author Affiliations
Kevin M. Monahan, KLA-Tencor Corp. (United States)
Scott M. Ashkenaz, KLA-Tencor Corp. (United States)
Xing Chen, KLA-Tencor Corp. (United States)
Patrick J. Lord, KLA-Tencor Corp. (United States)
Mark Andrew Merrill, KLA-Tencor Corp. (United States)
Rich Quattrini, KLA-Tencor Corp. (United States)
James N. Wiley, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 3998:
Metrology, Inspection, and Process Control for Microlithography XIV
Neal T. Sullivan, Editor(s)

© SPIE. Terms of Use
Back to Top