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Proceedings Paper

Reduction of wafer-scale error between DI and FI in multilevel metallization by adjusting edge detection method
Author(s): Sang-Gil Bae; Young-Keun Kim; Ki-Yeop Park; Jin-Soo Kim; Won-Kyu Lee; S.W. Lee; Dai-Hoon Lee
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Paper Abstract

As the integration density of VLSI device increases, the overlay accuracy in the photolithography becomes more and more important. In the sub-quarter micron technology, the registration budget is less than 70 nm. Registration error can be induced by the repeatability error of alignment sensor, mask fabrication error, tool induced shift, process induced shift, and so on. One of these misregistration error sources, overlay parameter difference between DI and FI, can cause significant damage to the device because, in most cases, overlay accuracy is checked only in the mask step. In this paper, we studied the relationship of the Edge Detection Algorithm (EDA) and the overlay mark structure to the wafer scale difference.

Paper Details

Date Published: 2 June 2000
PDF: 10 pages
Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); doi: 10.1117/12.386502
Show Author Affiliations
Sang-Gil Bae, Hyundai Electronics Industries Co., Ltd. (South Korea)
Young-Keun Kim, Hyundai Electronics Industries Co., Ltd. (South Korea)
Ki-Yeop Park, Hyundai Electronics Industries Co., Ltd. (South Korea)
Jin-Soo Kim, Hyundai Electronics Industries Co., Ltd. (South Korea)
Won-Kyu Lee, Hyundai Electronics Industries Co., Ltd. (South Korea)
S.W. Lee, Hyundai Electronics Industries Co., Ltd. (South Korea)
Dai-Hoon Lee, Hyundai Electronics Industries Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 3998:
Metrology, Inspection, and Process Control for Microlithography XIV
Neal T. Sullivan, Editor(s)

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