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Proceedings Paper

Merged CCD/SOI-CMOS technology
Author(s): Vyshi Suntharalingam; Barry E. Burke; J. A. Burns; M. J. Cooper; Craig L. Keast
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Paper Abstract

In this paper we describe a new technology which fabricates CCDs and fully depleted silicon on insulator CMOS circuits on the same 150-mm silicon wafer. We present results from 7.5 X 7.5-micrometers 2 and 15 X 15-micrometers 2-pixel imagers that are 512 X 512 frame transfer devices. The 7.5-micrometers -pixel device exhibits a charge handling capacity in excess of 100,000 electrons at 3.3 V and the 15-micrometers - pixel device exhibits a charge-transfer efficiency over 99.998%. In addition, we demonstrate functional SOI CMOS ring oscillators with delay of 47 ps/stage at 3.3 V and 68 ps/stage at 2 V.

Paper Details

Date Published: 15 May 2000
PDF: 8 pages
Proc. SPIE 3965, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications, (15 May 2000); doi: 10.1117/12.385466
Show Author Affiliations
Vyshi Suntharalingam, MIT Lincoln Lab. (United States)
Barry E. Burke, MIT Lincoln Lab. (United States)
J. A. Burns, MIT Lincoln Lab. (United States)
M. J. Cooper, MIT Lincoln Lab. (United States)
Craig L. Keast, MIT Lincoln Lab. (United States)


Published in SPIE Proceedings Vol. 3965:
Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications
Morley M. Blouke; Nitin Sampat; Thomas Yeh; Nitin Sampat; George M. Williams; Thomas Yeh, Editor(s)

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