Share Email Print
cover

Proceedings Paper

New ultrathin 3D integration technique: technological and thermal investigations
Author(s): Stephane Pinel; Josiane Tasselli; Antoine Marty; Jean-Pierre Bailbe; Eric Beyne; Rita Van Hoof; Santiago Marco; Sergio Leseduarte; Olivier Vendier; Augustin Coello-Vera
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.

Paper Details

Date Published: 10 April 2000
PDF: 9 pages
Proc. SPIE 4019, Design, Test, Integration, and Packaging of MEMS/MOEMS, (10 April 2000); doi: 10.1117/12.382262
Show Author Affiliations
Stephane Pinel, Lab. d'Analyse et d'Architecture des Systemes (France)
Josiane Tasselli, Lab. d'Analyse et d'Architecture des Systemes (France)
Antoine Marty, Lab. d'Analyse et d'Architecture des Systemes (France)
Jean-Pierre Bailbe, Lab. d'Analyse et d'Architecture des Systemes (France)
Eric Beyne, IMEC (Belgium)
Rita Van Hoof, IMEC (Belgium)
Santiago Marco, Univ. de Barcelona (Spain)
Sergio Leseduarte, Univ. de Barcelona (Spain)
Olivier Vendier, Alcatel Space Industries (France)
Augustin Coello-Vera, Alcatel Space Industries (France)


Published in SPIE Proceedings Vol. 4019:
Design, Test, Integration, and Packaging of MEMS/MOEMS
Bernard Courtois; Selden B. Crary; Kaigham J. Gabriel; Jean Michel Karam; Karen W. Markus; Andrew A. O. Tay, Editor(s)

© SPIE. Terms of Use
Back to Top