Share Email Print
cover

Proceedings Paper

Real-time FPGA architectures for computer vision
Author(s): Miguel Arias-Estrada; Cesar Torres-Huitzil
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

Paper Details

Date Published: 21 March 2000
PDF: 10 pages
Proc. SPIE 3966, Machine Vision Applications in Industrial Inspection VIII, (21 March 2000); doi: 10.1117/12.380096
Show Author Affiliations
Miguel Arias-Estrada, Instituto Nacional de Astrofisica, Optica y Electronica (Mexico)
Cesar Torres-Huitzil, Instituto Nacional de Astrofisica, Optica y Electronica (Mexico)


Published in SPIE Proceedings Vol. 3966:
Machine Vision Applications in Industrial Inspection VIII
Kenneth W. Tobin; John C. Stover, Editor(s)

© SPIE. Terms of Use
Back to Top