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Proceedings Paper

Optimization of 2D median filtering algorithm for VLIW architecture
Author(s): Chang Y. Choo; Ming Tang
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Paper Abstract

Recently, several commercial DSP processors with VLIW (Very Long Instruction Word) architecture were introduced. The VLIW architectures offer high performance over a wide range of multimedia applications that require parallel processing. In this paper, we implement an efficient 2D median filter for VLIW architecture, particularly for Texas Instrument C62x VLIW architecture. Median filter is widely used for filtering the impulse noise while preserving edges in still images and video. The efficient median filtering requires fast sorting. The sorting algorithms were optimized using software pipelining and loop unrolling to maximize the use of the available functional units while meeting the data dependency constraints. The paper describes and lists the optimized source code for the 3 X 3 median filter using an enhanced selection sort algorithm.

Paper Details

Date Published: 29 December 1999
PDF: 10 pages
Proc. SPIE 3970, Media Processors 2000, (29 December 1999); doi: 10.1117/12.375246
Show Author Affiliations
Chang Y. Choo, San Jose State Univ. and Altera Corp. (United States)
Ming Tang, San Jose State Univ. (United States)

Published in SPIE Proceedings Vol. 3970:
Media Processors 2000
Sethuraman Panchanathan; V. Michael Bove Jr.; Subramania I. Sudharsanan, Editor(s)

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