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Proceedings Paper

Parallel architecture for the computation of NURBS surfaces
Author(s): Montserrat Boo; Javier Diaz Bruguera; Emilio Lopez-Zapata
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Paper Abstract

B-Splines computation for iterative 3D geometric modeling and graphic animation sessions imply large computational requirements which suggests the utilization of high- performance VLSI architectures. In this paper we describe an architecture for the computation of rational B-Spline surfaces and their derivatives. The architecture is based on the utilization of a highly regular and modular structure, suitable for VLSI implementation, which permits the reconfiguration of the system when no derivatives are required. A new scheduling system permits a fully exploited system in both configuration modes, through the understanding of the parallel structure of the algorithm.

Paper Details

Date Published: 29 December 1999
PDF: 12 pages
Proc. SPIE 3970, Media Processors 2000, (29 December 1999); doi: 10.1117/12.375243
Show Author Affiliations
Montserrat Boo, Univ. of Santiago de Compostela (Spain)
Javier Diaz Bruguera, Univ. of Santiago de Compostela (Spain)
Emilio Lopez-Zapata, Univ. of Malaga (Spain)

Published in SPIE Proceedings Vol. 3970:
Media Processors 2000
Sethuraman Panchanathan; V. Michael Bove; Subramania I. Sudharsanan, Editor(s)

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