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Proceedings Paper

Software implementation of MPEG-2 decoder on VLIW media processors
Author(s): Hiroki Mizosoe; Yoochang Jung; Donglok Kim; Woobin Lee; Yongmin Kim
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Paper Abstract

We have implemented software MPEG-2 decoders on two mediaprocessors, Texas Instruments TMS320C80 and Hitachi/Equator Technologies MAP1000, On the TMS320C80, its small instruction cache and inefficient advanced Digital Signal Processor architecture for bitstream parsing resulted in the performance of about twelve frames per second for 5 Mbit/s MPEG-2 bitstreams on a 50-MHz TMS320C80. On the other hand, the MPEG-2 decoder implemented on a 200-MHz MAP1000 achieved real-time performance in decoding of MPML bitstreams. The implementation details, such as tight loops and data flow, are presented. We also compare the architectural features of the two mediaprocessors in performing the MPEG-2 decoding. The instruction set specifically targeted for multimedia processing, better instruction cache utilization, and an independent variable length decoder are among the advantages of MAP1000.

Paper Details

Date Published: 29 December 1999
PDF: 11 pages
Proc. SPIE 3970, Media Processors 2000, (29 December 1999); doi: 10.1117/12.375240
Show Author Affiliations
Hiroki Mizosoe, Univ. of Washington (Japan)
Yoochang Jung, Univ. of Washington (United States)
Donglok Kim, Univ. of Washington (United States)
Woobin Lee, Univ. of Washington (United States)
Yongmin Kim, Univ. of Washington (United States)

Published in SPIE Proceedings Vol. 3970:
Media Processors 2000
Sethuraman Panchanathan; V. Michael Bove Jr.; Subramania I. Sudharsanan, Editor(s)

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