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Proceedings Paper

Memory chip packaging: an enabling technology for high-performance recce systems
Author(s): Bruce Kaufman
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Paper Abstract

New generation airborne recce systems, for both manned and unmanned aircraft, are faced with dramatically increased performance requirements, along with calls for reduced costs, faster time to deployment, lower weight and lower physical volume. Concurrently, recording rates are moving to >1GByte/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of GBytes. Even with memory chip densities at present day 64Mb, such capacities require many thousands of chips. The demands on packaging technology are daunting. This paper will consider the basis for these capacities, review approaches to memory chip packaging and offer a discussion of physical envelope trade-offs in achieving the required objective of packaging this large number of chips in a practical, flyable, cost-effective envelope.

Paper Details

Date Published: 7 December 1999
PDF: 5 pages
Proc. SPIE 3751, Airborne Reconnaissance XXIII, (7 December 1999); doi: 10.1117/12.372647
Show Author Affiliations
Bruce Kaufman, Controlex Corp. (United States)


Published in SPIE Proceedings Vol. 3751:
Airborne Reconnaissance XXIII
Wallace G. Fishell, Editor(s)

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