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Proceedings Paper

Automatic verification of asynchronous circuits using modified STG control graph
Author(s): Eddie M.C. Wong; Jie Gong
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Paper Abstract

Verifying the correctness of asynchronous sequential circuits is one of the most important tasks in asynchronous design. However, the absence of the global clock and the variation of gate delays in asynchronous circuits make the verification a formidable task. In this paper, a method that can perform efficient timing analysis of gate-level implementation of asynchronous circuits is presented. The method is based on specific behavior given by the Signal Transition Graph (STG). By modifying the STG into the STG control graph, the circuit can be simulated correctly with automatic test generation. The ternary logic is introduced in order to describe the behaviors of gates with bounded inertial delays. The program is written in VHDL. Lastly in this paper, one of the many simulation results to detect hazards is presented.

Paper Details

Date Published: 8 October 1999
PDF: 8 pages
Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); doi: 10.1117/12.368427
Show Author Affiliations
Eddie M.C. Wong, Nanyang Technological Univ. (Singapore)
Jie Gong, Nanyang Technological Univ. (Singapore)

Published in SPIE Proceedings Vol. 3893:
Design, Characterization, and Packaging for MEMS and Microelectronics
Bernard Courtois; Serge N. Demidenko, Editor(s)

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