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Proceedings Paper

Development of power accumulation-type SiC MOSFET
Author(s): Handoko Linewih; Sima Dimitrijev; H. Barry Harrison
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Paper Abstract

A new structure of SiC ACCUFET MOSFET for high power applications have been proposed and analyzed by simulation. The new MOSFET has an n-type ion implanted trench region and a MOS structure consisting of a thin surface layer of epitaxially grown n-type SiC. The current flows through then-type ion implanted region, then via accumulation channel of electrons defined in the epitaxially grown SiC surface layer. The thickness and doping of the n-type surface and p-type base epitaxially grown layers control the channel conditions. At zero gate bias the channel is fully depleted by the built-in fields of SiC p-base layer and the gate electrode resulting in a normally off device with the drain voltage supported by the n-drift region. Moreover, this designed structure fully addresses most of the open issues related to the MOS interface problems, i.e. low channel mobility and high electric field in the gate oxide of the MOS structure. 2D numerical simulations demonstrate that the optimized designed structure can withstand the blocking voltage of more than 1000 V, and a low specific on- resistance. The analytically calculated and simulated result son specific on-resistance of the optimized structure show as low a s 19.3 (Omega) cm2 specific on resistance can achieved with low gate bias of 5V.

Paper Details

Date Published: 8 October 1999
PDF: 9 pages
Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); doi: 10.1117/12.368421
Show Author Affiliations
Handoko Linewih, Griffith Univ. (Australia)
Sima Dimitrijev, Griffith Univ. (Australia)
H. Barry Harrison, Griffith Univ. (Australia)


Published in SPIE Proceedings Vol. 3893:
Design, Characterization, and Packaging for MEMS and Microelectronics
Bernard Courtois; Serge N. Demidenko, Editor(s)

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