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Proceedings Paper

Fast on-line multiplication units using LSA organization
Author(s): Alexandre F. Tenca; Milos D. Ercegovac; Marianne E. Louie
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Paper Abstract

This paper presents the application of the Linear Sequential Array (LSA) retiming approach, developed for conventional digit- recurrence algorithms, to on-line multiplication. The result is a modular and fast pipelined structure which due to a small constant fan-out and cycle time independent of precision is suitable for FPGA implementation. First we present the basics of on-line multiplication, and determine data dependencies according to the LSA design methodology. Based on these dependencies we redesign the traditional on-line multiplier to obtain the LSA structure. Since in DSP applications one of the multiplier operands is fixed for a long sequence of operations, we briefly present a parallel-serial multiplication unit that receives one of the operands in parallel and the other operand in Most-Significant-Digit-First format. Performance and area results are provided for the LSA on-line multiplier design and then compared with the conventional on-line design, using Xilinx FPGAs as the target technology.

Paper Details

Date Published: 2 November 1999
PDF: 10 pages
Proc. SPIE 3807, Advanced Signal Processing Algorithms, Architectures, and Implementations IX, (2 November 1999); doi: 10.1117/12.367682
Show Author Affiliations
Alexandre F. Tenca, Oregon State Univ. (United States)
Milos D. Ercegovac, Univ. of California/Los Angeles (United States)
Marianne E. Louie, Univ. of California/Los Angeles (United States)

Published in SPIE Proceedings Vol. 3807:
Advanced Signal Processing Algorithms, Architectures, and Implementations IX
Franklin T. Luk, Editor(s)

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