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Proceedings Paper

10-GOPS transversal filter and error table compensator
Author(s): Andrew J. Beaumont-Smith; Cheng-Chew Lim; John Tsimbinos; Warren Marwood; Neil Burgess
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Paper Abstract

A cascadable 10GOPS transversal filter chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti- symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4 - 2 compressors to reduce the transistor count. The chip was fabricated in a 0.35 micrometer CMOS process, measures 3.1 X 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz (200 MSa/s throughput). An error table compensator system using a lookup table has been built using the transversal filter programmed as a wideband differentiator with some additional on chip circuits including delays and an adder. An external memory stores the error table. The error table technique is capable of providing between 7 to 15 dB improvement in the dynamic range of typical 100 Ms/s A/D converters. An application to pulse shaping of high chip rate spread spectrum signals is also discussed.

Paper Details

Date Published: 2 November 1999
PDF: 7 pages
Proc. SPIE 3807, Advanced Signal Processing Algorithms, Architectures, and Implementations IX, (2 November 1999); doi: 10.1117/12.367632
Show Author Affiliations
Andrew J. Beaumont-Smith, Univ. of Adelaide (Australia)
Cheng-Chew Lim, Univ. of Adelaide (Australia)
John Tsimbinos, Defence Science and Technology Organisation (Australia)
Warren Marwood, Defence Science and Technology Organisation (Australia)
Neil Burgess, Univ. of Adelaide (United Kingdom)


Published in SPIE Proceedings Vol. 3807:
Advanced Signal Processing Algorithms, Architectures, and Implementations IX
Franklin T. Luk, Editor(s)

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