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Proceedings Paper

Architectures for parallel DSP-based adaptive optics feedback control
Author(s): Daniel F. McCarthy
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Paper Abstract

We have developed a digital image processing system for real-time digital image processing feedback control of adaptive optics systems and simulation of optical image processing algorithms. The system uses multi-computer architecture to capture data from an imaging device such as a charge coupled device camera, process the image data, and control a spatial light-modulator, typically a liquid crystal modulator or a micro-electro mechanical system. The system is a Windows NT Pentium-based system combined with a commercial off-the-shelf peripheral component interconnect bus multi-processor system. The multi-processor is based on the Analog Devices super Harvard architecture computer (SHARC) processor, and field programmable gate arrays (FPGAs). The SHARCs provide a scalable reconfigurable C language-based digital signal processing (DSP) development environment. The FPGAs are typically used as reprogrammable interface controllers designed to integrate several off-the- shelf and custom imagers and light modulators into the system. The FPGAs can also be used in concert with the SHARCs for implementation of application-specific high-speed DSP algorithms.

Paper Details

Date Published: 3 November 1999
PDF: 7 pages
Proc. SPIE 3760, High-Resolution Wavefront Control: Methods, Devices, and Applications, (3 November 1999); doi: 10.1117/12.367581
Show Author Affiliations
Daniel F. McCarthy, Army Research Lab. (United States)


Published in SPIE Proceedings Vol. 3760:
High-Resolution Wavefront Control: Methods, Devices, and Applications
John D. Gonglewski; Mikhail A. Vorontsov, Editor(s)

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