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Proceedings Paper

3D packaging technology for vision CMOS VLSI: review and performance evaluation
Author(s): Amine Bermak; Abdesselam Bouzerdoum; Kamran Eshraghian
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Paper Abstract

In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.

Paper Details

Date Published: 29 September 1999
PDF: 9 pages
Proc. SPIE 3891, Electronics and Structures for MEMS, (29 September 1999); doi: 10.1117/12.364446
Show Author Affiliations
Amine Bermak, Edith Cowan Univ. (Australia)
Abdesselam Bouzerdoum, Edith Cowan Univ. (Australia)
Kamran Eshraghian, Edith Cowan Univ. (Australia)


Published in SPIE Proceedings Vol. 3891:
Electronics and Structures for MEMS
Neil W. Bergmann; Olaf Reinhold; Norman C. Tien, Editor(s)

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