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Proceedings Paper

Compact two-step parallel modified-signed-digit adder/substractor based on binary logic operations using electron-trapping devices
Author(s): Guoqiang Li; Feng Qian; Hao Ruan; Liren Liu
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Paper Abstract

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary operations regardless of the sign of the input digits. The optical implementation and experimental demonstration using an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinatorial logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general- purpose, simple to align and has a high signal-to-noise ratio.

Paper Details

Date Published: 1 October 1999
PDF: 9 pages
Proc. SPIE 3805, Photonic Devices and Algorithms for Computing, (1 October 1999); doi: 10.1117/12.364005
Show Author Affiliations
Guoqiang Li, Shanghai Institute of Optics and Fine Mechanics (United States)
Feng Qian, Shanghai Institute of Optics and Fine Mechanics (China)
Hao Ruan, Shanghai Institute of Optics and Fine Mechanics (China)
Liren Liu, Shanghai Institute of Optics and Fine Mechanics (China)


Published in SPIE Proceedings Vol. 3805:
Photonic Devices and Algorithms for Computing
Khan M. Iftekharuddin; Abdul Ahad Sami Awwal, Editor(s)

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