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Proceedings Paper

Fatal defect detection from visual abnormalities of logic LSI using IDDQ
Author(s): Masaru Sanada; Hiromu Fujioka
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Paper Abstract

Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the definition area, and by locating test vector related to abnormal IDDQ, following which fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.

Paper Details

Date Published: 27 August 1999
PDF: 12 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361355
Show Author Affiliations
Masaru Sanada, NEC Corp. and Osaka Univ. (Japan)
Hiromu Fujioka, Osaka Univ. (Japan)

Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

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