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Proceedings Paper

Practical manufacturing technique for reducing charge-induced gate oxide degradation during ion implantation
Author(s): Kenneth G. Moerschel; W. A. Possanza; James Sung; M. A. Prozonic; T. Long; J. Pavlo; T. Chrapacz
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Paper Abstract

Test wafers were fabricated to evaluate leakage and charge-to- breakdown (Qbd) of gate oxide capacitor structures subjected to high dose ion implantation. Both insulating and partially conductive (polysilicon) films were present on the wafer backsides during implantation, and the ion implanter's electron flood gun current was varied to optimize the final capacitor leakage yield. Relative to a conductive (polysilicon) backside film present during ion implantation, a backside 1700 Angstrom LPCVD Si3N4 layer provided significantly improved gate oxide protection, after optimization of the electron flood gun current. The backside LPCVD Si3N4 had no discernible effect on the Qbd of the capacitors after high dose ion implantation.

Paper Details

Date Published: 27 August 1999
PDF: 12 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361350
Show Author Affiliations
Kenneth G. Moerschel, Lucent Technologies/Bell Labs. (United States)
W. A. Possanza, Lucent Technologies/Bell Labs. (United States)
James Sung, Vanguard Semiconductor International (Taiwan)
M. A. Prozonic, Lucent Technologies/Bell Labs. (United States)
T. Long, Lucent Technologies/Bell Labs. (United States)
J. Pavlo, Lucent Technologies/Bell Labs. (United States)
T. Chrapacz, Lucent Technologies/Bell Labs. (United States)


Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

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