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Proceedings Paper

Influence of metal deposition temperature on deep-submicrometer metal lithography
Author(s): Vijaya Subramaniam; Daniel D. Siems; Martin P. Karnett; Sonu Ram Maheshwary; Harlan Sur
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Paper Abstract

This paper describes some of the methodologies employed to achieve rapid yield learning on 0.25 micrometer, three-layer metal CMOS process. This includes: (1) design of a manufacturing-representative process qualification vehicle which readily lends itself to failure analysis and (2) the tools employed to define and resolve yield-limiting mechanisms in an expeditious manner. Electrical SRAM bitmapping, physical failure analysis and in-line inspection were used to identify and resolve a primary failure mechanism on the 0.25 micrometer, CMOS process. In this instance, small metal landing pads, which are typically used to support stacked contact/via process architectures, were shown to lose adhesion and topple over at various locations within the SRAM circuitry. Further in-process investigations showed that this problem could be modulated and eliminated through changes in the metal deposition temperature. Lowering the metal deposition temperature eliminated this problem and led to improvements in both memory and logic yields.

Paper Details

Date Published: 27 August 1999
PDF: 8 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361344
Show Author Affiliations
Vijaya Subramaniam, VLSI Technology, Inc./Philips Semiconductor (United States)
Daniel D. Siems, VLSI Technology, Inc./Philips Semiconductor (United States)
Martin P. Karnett, VLSI Technology, Inc./Philips Semiconductor (United States)
Sonu Ram Maheshwary, VLSI Technology, Inc./Philips Semiconductor (United States)
Harlan Sur, VLSI Technology, Inc./Philips Semiconductor (United States)


Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

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