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Proceedings Paper

Innovating SRAM design and test program for fast process-related defect recognition and failure analysis
Author(s): Peter Coppens; Guido Vanhorebeek; Eddy De Backer; Xiao Jie Yuan
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Paper Abstract

A special SRAM has been designed as a yield enhancement vehicle in a 0.35 micrometer CMOS technology. Extra design rules were added to encourage process defects on certain places and discourage them on others. From the failure signature of a memory cell (0 or 1 failure) and its failure extent (single cell, double cell, bitline, wordline, ...) one can uniquely determine the process related cause of the failure. A dedicated test program has been developed to find the most common failures in a memory cell (e.g. floating bitline, bitline shorted to ground or Vdd, shorts between the nodes of the cell, ...). The innovating characteristics of the design allow to link these failures in an SRAM with high probability to a process related defect and its location within the memory cell. By simply testing the SRAM the main cause of failure can be found which can help to drive yield improvement, without doing intensive failure analysis. In this paper the design philosophy and the test methodology of this SRAM are described, illustrated with some examples of process related defects that proved the usefulness and the strength of the design and the test program.

Paper Details

Date Published: 27 August 1999
PDF: 8 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361343
Show Author Affiliations
Peter Coppens, Alcatel Microelectronics (Belgium)
Guido Vanhorebeek, IMEC (Belgium)
Eddy De Backer, Alcatel Microelectronics (Belgium)
Xiao Jie Yuan, IMEC (Belgium)


Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

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