Share Email Print

Proceedings Paper

Frequency distribution modeling for high-speed microprocessors using on-chip ring oscillators
Author(s): John M. Carulli; Derek C. Wrobbel; Aswin Mehta; Kenneth E. Krause; Brad E. Campbell; Fred A. Valente
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

It is critical for success in the microprocessor business to understand the relationship between yield and speed- performance. This paper outlines a method for modeling device speed distribution and yield using on-chip ring-oscillator measurements. The modeling method is used in production on the UltraSPARCTM-II family of microprocessors. Lot-level speed distributions are predicted within 10% by speed-bin and quarterly distributions within 5% by speed-bin. Graphs are generated to show the relationship between business and process concerns.

Paper Details

Date Published: 27 August 1999
PDF: 10 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361341
Show Author Affiliations
John M. Carulli, Texas Instruments Inc. (United States)
Derek C. Wrobbel, Texas Instruments Inc. (United States)
Aswin Mehta, Texas Instruments Inc. (United States)
Kenneth E. Krause, Texas Instruments Inc. (United States)
Brad E. Campbell, Texas Instruments Inc. (United States)
Fred A. Valente, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

© SPIE. Terms of Use
Back to Top