Share Email Print

Proceedings Paper

IMP copper seed layer formation with TaN barrier for deep submicron
Author(s): Babu Narayanan; Chao Yong Li; Kangsoo Lee; Bo Yu; Jun Jie Wu; Pang Dow Foo; Joseph Xie
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As the device dimension approaches to subquarter-micron, the scaling of geometry's causes an increase in interconnection resistance and current density. Copper is to replace the widely used aluminum, because of the low resistivity and resistance to electromigration. However due to the difficulty of dry etching of Cu, a damascene process is required, which needs a narrow gap filling process. But the step coverage of conventional sputtering if too poor to fill narrow gaps. Though the reflow process of sputtered Cu films is reported to improve the filling property, it is still difficult to fill high aspect ratio vias/trenches. This paper will discuss the continuous and conformal copper seed layer formation using Ionized Metal Plasma (IMP) technique for high aspect ratio vias, which is one of the key to void free electroplating of copper and for a Metal Organic Chemical Vapor Deposition (MOCVD) Cu gap filling with good adhesion. A copper seed layer of around 150 - 200 nm is deposited by IMP and to be followed by a thicker layer of MOCVD or electroplating. More over excellent bottom and side wall coverage was achieved on a patterned wafer with high aspect ratio vias/trenches. The key challenge here will be good adhesion and step coverage of Cu seed layer with the underlying barrier metal Ta/TaN, which is a good candidate of diffusion barrier for Cu. In overall the sheet resistance, adhesion, step coverage etc. will be discussed in the paper.

Paper Details

Date Published: 11 August 1999
PDF: 4 pages
Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); doi: 10.1117/12.360585
Show Author Affiliations
Babu Narayanan, Institute of Microelectronics (Singapore)
Chao Yong Li, Institute of Microelectronics (Singapore)
Kangsoo Lee, Institute of Microelectronics (Singapore)
Bo Yu, Institute of Microelectronics (Singapore)
Jun Jie Wu, Institute of Microelectronics (Singapore)
Pang Dow Foo, Institute of Microelectronics (Singapore)
Joseph Xie, Institute of Microelectronics (Singapore)

Published in SPIE Proceedings Vol. 3883:
Multilevel Interconnect Technology III
Mart Graef; Divyesh N. Patel, Editor(s)

© SPIE. Terms of Use
Back to Top