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Proceedings Paper

Challenges of damascene etching for copper interconnect
Author(s): Paul Kwok Keung Ho; Mei-Sheng Zhou; Subhash Gupta; Ramasamy Chockalingam; Jianxun Li; Ming Hui Fan
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Paper Abstract

Dual damascene patterning is essential for the integration of copper into a high performance interconnect, hence the etching process becomes the most important challenge. This paper described the work on the dual damascene etching. The three most common schemes for patterning the dual damascene structure are trench-first, via-first (also known as counter-bore) and self-aligned etchings. Although only self- aligned etching requires the insertion of a stop layer, the stop layer is crucial to all schemes for a better control of the etching uniformity. The impact of using a stop layer with every dual damascene scheme was investigated. Lithography plays an important role in damascene etching. The use of negative-tone photoresist for metal trench masking and the challenge of forming a residue-free damascene structure in the presence of a bottom anti- reflecting coating were discussed.

Paper Details

Date Published: 11 August 1999
PDF: 8 pages
Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); doi: 10.1117/12.360584
Show Author Affiliations
Paul Kwok Keung Ho, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Mei-Sheng Zhou, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Subhash Gupta, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Ramasamy Chockalingam, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Jianxun Li, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Ming Hui Fan, Chartered Semiconductor Manufacturing Ltd. (Singapore)


Published in SPIE Proceedings Vol. 3883:
Multilevel Interconnect Technology III
Mart Graef; Divyesh N. Patel, Editor(s)

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