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Proceedings Paper

Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation
Author(s): Dinesh Saigal; Gigi Lai; Lisa Yang; Jingang Su; Ken Ngan; Murali K. Narasimhan; Fusen E. Chen; Ajay Singhal; Dave Lopes; Sean Lian; Wanqing Cao; Kevin Tsai; Patrick Lo; Shih-Ked Lee; James Shih
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Paper Abstract

The effect of some key variables such as rapid thermal processing (RTP) temperature, substrate cleaning method and capping layers, on cobalt silicide formation has been investigated. The in-situ RF sputter etch is found to give a post RTP2 Rsh that is equivalent to a wet cleaned wafer. The temperature transformation curve of cobalt films, analyzed with Rsh data and XRD, reveal the formation of Co2Si-CoSi-CoSi2 phases in that order. The transformation curves of TiN capped films match those of blanket cobalt but the Ti capped films show the CoSi phase to be stable over a broader temperature range. There is no effect of dopants on the final cobalt disilicide Rsh values for either the single of polycrystalline substrates. Controlled oxygen leak studies in the RTP ambient reveal that the Rsh after RTP1 is degraded if a capping layer is not present. Electrical test results confirm the need for capping layers. This is indicated by lower Rsh and Rc values on both n+ and p+ junctions and poly structures. Furthermore the electrical results are comparable for Ti and TiN layers used as the cap films although the Rsh/Rc values are in general lower for the TiN capped films. Poly gate length vs Rsh plots show the extendibility of the capped cobalt silicide process to the 0.18 um node.

Paper Details

Date Published: 11 August 1999
PDF: 12 pages
Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); doi: 10.1117/12.360574
Show Author Affiliations
Dinesh Saigal, Applied Materials Inc. (United States)
Gigi Lai, Applied Materials Inc. (United States)
Lisa Yang, Applied Materials Inc. (United States)
Jingang Su, Applied Materials Inc. (United States)
Ken Ngan, Applied Materials Inc. (United States)
Murali K. Narasimhan, Applied Materials Inc. (United States)
Fusen E. Chen, Applied Materials Inc. (United States)
Ajay Singhal, Applied Materials Inc. (United States)
Dave Lopes, Applied Materials Inc. (United States)
Sean Lian, Integrated Device Technology (United States)
Wanqing Cao, Integrated Device Technology (United States)
Kevin Tsai, Integrated Device Technology (United States)
Patrick Lo, Integrated Device Technology (United States)
Shih-Ked Lee, Integrated Device Technology (United States)
James Shih, Integrated Device Technology (United States)


Published in SPIE Proceedings Vol. 3883:
Multilevel Interconnect Technology III
Mart Graef; Divyesh N. Patel, Editor(s)

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