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Proceedings Paper

Stress minimization of corner rounding process during STI
Author(s): Christopher S. Olsen; Faran Nouri; Mark E. Rubin; Olivier Laparra; Gregory S. Scott
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Paper Abstract

For sub 0.25 micron CMOS processes, Shallow Trench Isolation (STI) is required because of its planarity, high packing density and low junction edge capacitance. After trench etch in the STI process, the top corner of the trench must be rounded in order to achieve stable device performance, reduce inverse narrow width effects and maintain good gate oxide integrity. Several methods of round in the trench corners have been proposed. A post-CMP oxidation step to round the top corner trench has been shown to consume too much of the silicon active area and may not be suitable for sub-0.18micrometers technologies. Furthermore, the post-CMP oxidation can generate a lot of stress even at high temperatures. It has been shown that a 50 nm radius of curvature provides stable device data and a good gate oxide integrity with minimum consumption of the active area. In this paper, we have shown that this radius can be achieved with minimal stress generation using a properly optimized rapid thermal oxidation before oxide fill. Through both 2D oxidation modeling and experimental verification we have shown that an optimum oxidation temperature can be found when coupled with an undercut of the buffer oxide under the silicon nitride mask. Temperature is the primary parameter for rounding of the top corner during oxidation while undercut of the buffer oxide lowers the minimum temperature for a given rounding. A 50 nm radius of curvature can be achieved by the balance of the two parameters. This radius of curvature has been shown to suitable for 0.15 micron technology and beyond.

Paper Details

Date Published: 1 September 1999
PDF: 9 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360555
Show Author Affiliations
Christopher S. Olsen, VLSI Technology, Inc. (United States)
Faran Nouri, VLSI Technology, Inc. (United States)
Mark E. Rubin, VLSI Technology, Inc. (United States)
Olivier Laparra, VLSI Technology, Inc. (United States)
Gregory S. Scott, VLSI Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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