Share Email Print

Proceedings Paper

Gate-length- and threshold-voltage-dependent nonlinearity in the hot carrier DC lifetime extrapolation for sub-100-nm NMOS devices
Author(s): Sejal N. Chheda; Navakanta Bhat; Paul Tsui; Suzanne Gonzales; Nigel Cave; Chong-Cheng Fu; Fred Huang; Amit Nangia; Philip Sung-Joon Choi; Sean Collins
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper, we discuss the issues involved in the DC hot carrier lifetime extrapolation of sub 100nm NMOS transistors. We look at device degradation due to hot- carrier injection in NMOS transistors with 20 angstrom and 25 angstrom thermal and nitrided oxide gate dielectrics. Stress conditions such as Vg < Vt, Vg > Vt, Vd equals Vd, and Vg at Isubmax are evaluated. Previously, devices greater than 100nm gate length had highest hot carrier degradation at Vg at Isubmax and 1/Vdd linear extrapolation from accelerated stressing condition to operation condition was able to estate the DC lifetime. However, we show that the conventional extrapolation results in a nonlinear fit for devices with gate length

Paper Details

Date Published: 1 September 1999
PDF: 11 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360551
Show Author Affiliations
Sejal N. Chheda, Motorola (United States)
Navakanta Bhat, Indian Institute of Science/Bangalore (United States)
Paul Tsui, Self-employed (United States)
Suzanne Gonzales, Motorola (United States)
Nigel Cave, Motorola (United States)
Chong-Cheng Fu, Motorola (United States)
Fred Huang, Motorola (United States)
Amit Nangia, Motorola (United States)
Philip Sung-Joon Choi, Motorola (United States)
Sean Collins, Motorola (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top