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Proceedings Paper

Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-um surface-channel PMOS devices
Author(s): Gregory S. Scott; Samar K. Saha; Christopher S. Olsen; Faran Nouri; Jeffrey Lutze; Mark E. Rubin; Martin Manley
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Paper Abstract

Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (Vt) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in Vt. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS Vt scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS Vt we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.

Paper Details

Date Published: 1 September 1999
PDF: 9 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360543
Show Author Affiliations
Gregory S. Scott, VLSI Technology, Inc. (United States)
Samar K. Saha, VLSI Technology, Inc. (United States)
Christopher S. Olsen, VLSI Technology, Inc. (United States)
Faran Nouri, VLSI Technology, Inc. (United States)
Jeffrey Lutze, VLSI Technology, Inc. (United States)
Mark E. Rubin, VLSI Technology, Inc. (United States)
Martin Manley, VLSI Technology, Inc. (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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