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Proceedings Paper

Mismatch characterization and modelization of deep-submicron CMOS transistors
Author(s): Helene Thibieroz; Alain Duvallet
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Paper Abstract

The characterization of nmos transistor mismatch for three different standard CMOS technologies is presented. Different methods for matching parameter extraction have been compared. By studying the correlation of these mismatch parameters, an optimized set has been generated. Using these parameters, mismatch of drain current can be predicted and modeled. The model accuracy has been studied. Finally, by comparing the mismatch model found for crucial parameters and for each technology, the impact of gate oxide thickness on mismatch characteristics has been observed.

Paper Details

Date Published: 1 September 1999
PDF: 8 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360542
Show Author Affiliations
Helene Thibieroz, Motorola (United States)
Alain Duvallet, Motorola (United States)


Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

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