Share Email Print

Proceedings Paper

Scaling the gate dielectric
Author(s): David J. Eaglesham
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The gate dielectric is arguably the biggest challenge facing the physical scaling of the MOSFET. The alternatives to continued scaling of SiO2 include radical departures from standard process flows and very challenging new materials issues. In the short term, the industry continues to pursue improvements to the reliability and tunneling performance of silicon-dioxide. New data on reliability suggests that SiO2 as thin as 1.6nm may achieve acceptable reliability in the field. Beyond SiO2, there is no material which has yet demonstrated comparable reliability or interface-state-density. The most promising approach involves using sandwiched high-k material, with thin SiO2 at both interfaces. Either Ta2O5 or TiO2 may be suitable in structures of this type.

Paper Details

Date Published: 1 September 1999
PDF: 6 pages
Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); doi: 10.1117/12.360539
Show Author Affiliations
David J. Eaglesham, Lucent Technologies/Bell Labs. (United States)

Published in SPIE Proceedings Vol. 3881:
Microelectronic Device Technology III
David Burnett; Toshiaki Tsuchiya, Editor(s)

© SPIE. Terms of Use
Back to Top