Share Email Print
cover

Proceedings Paper

Image processing coprocessor implementation for Xilinx XC6000 series FPGAs
Author(s): Khaled Benkrid; K. Alotaibi; Danny Crookes; Ahmed Bouridane; Abdsamad Benkrid
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents an Image Processing Coprocessor implementation for XC6000 series FPGAs. The FPGA acts as a semi-autonomous abstract coprocessor carrying out image processing operational independently. This paper outlines the main structure of the image processing coprocessor in addition to its high level programming environment. The environment provides a library of very high level, parametrized architecture descriptions which are scaleable and general.

Paper Details

Date Published: 26 August 1999
PDF: 8 pages
Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359529
Show Author Affiliations
Khaled Benkrid, Queen's Univ. of Belfast (United Kingdom)
K. Alotaibi, Queen's Univ. of Belfast (United Kingdom)
Danny Crookes, Queen's Univ. of Belfast (United Kingdom)
Ahmed Bouridane, Queen's Univ. of Belfast (United Kingdom)
Abdsamad Benkrid, Queen's Univ. of Belfast (United Kingdom)


Published in SPIE Proceedings Vol. 3844:
Reconfigurable Technology: FPGAs for Computing and Applications
John Schewel; Peter M. Athanas; Steven A. Guccione; Stefan Ludwig; John T. McHenry, Editor(s)

© SPIE. Terms of Use
Back to Top