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Proceedings Paper

IP validation for FPGAs using Hardware Object Technology(tm)
Author(s): Steve Casselman; John Schewel; Christophe Beaumont
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Paper Abstract

We introduce in this paper the process of validation applied to digital designs in FPGAs. It allows the designer the ability to test his/her implementation using the real data of the application and providing real results. With such real data, it becomes easier to identify where the error occurs and then to understand it.

Paper Details

Date Published: 26 August 1999
PDF: 6 pages
Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); doi: 10.1117/12.359525
Show Author Affiliations
Steve Casselman, Virtual Computer Corp. (United States)
John Schewel, Virtual Computer Corp. (United States)
Christophe Beaumont, Virtual Computer Corp. (United States)

Published in SPIE Proceedings Vol. 3844:
Reconfigurable Technology: FPGAs for Computing and Applications
John Schewel; Peter M. Athanas; Steven A. Guccione; Stefan Ludwig; John T. McHenry, Editor(s)

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