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Proceedings Paper

Characterization and reliability of CMOS microstructures
Author(s): Gary K. Fedder; Ronald D. Shawn Blanton
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Paper Abstract

This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

Paper Details

Date Published: 18 August 1999
PDF: 8 pages
Proc. SPIE 3880, MEMS Reliability for Critical and Space Applications, (18 August 1999); doi: 10.1117/12.359362
Show Author Affiliations
Gary K. Fedder, Carnegie Mellon Univ. (United States)
Ronald D. Shawn Blanton, Carnegie Mellon Univ. (United States)


Published in SPIE Proceedings Vol. 3880:
MEMS Reliability for Critical and Space Applications
Russell A. Lawton; William M. Miller; Gisela Lin; Rajeshuni Ramesham, Editor(s)

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