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Proceedings Paper

High-speed alignment simulator for Nikon steppers
Author(s): Derek P. Coon; Arun A. Aiyer; Henry K. Chau; Hiroshi Ooki
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Paper Abstract

It is an unfortunate fact that most wafer processing steps degrade the quality of the stepper alignment marks rather than improve it. One example is the severe planarization requirements used in many VLSI processes. Furthermore, process development time, especially with respect to wafer alignment, has been reduced due to fab streamlining and cost of ownership issues. With these problems in mind Nikon has developed a commercially available alignment simulator to reduce stepper usage in alignment process development. The simulator can simulate Nikon's three different wafer alignment sensor and has five different simulation modes. The simulated alignment mark can have up to ten different process layers, the thicknesses of which can be varied simultaneously if need be. In addition, the geometry of each process layer can be made quite intricate so that complicated processes can be simulate.d The simulator uses scalar diffraction theory for high speed calculations, but which is still accurate when the mark width is larger than optimization which previously took weeks can now be done in days.

Paper Details

Date Published: 26 July 1999
PDF: 11 pages
Proc. SPIE 3679, Optical Microlithography XII, (26 July 1999); doi: 10.1117/12.354333
Show Author Affiliations
Derek P. Coon, Nikon Research Corp. of America (United States)
Arun A. Aiyer, Nikon Research Corp. of America (United States)
Henry K. Chau, Nikon Research Corp. of America (United States)
Hiroshi Ooki, Nikon Research Corp. of America (United States)


Published in SPIE Proceedings Vol. 3679:
Optical Microlithography XII
Luc Van den Hove, Editor(s)

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