Share Email Print
cover

Proceedings Paper

Ultrahigh-performance image processing architectures for hardware-in-the-loop testing
Author(s): Allan J. Cantle; Malachy Devlin; Eric Lord
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Synthetic scene generation systems require huge computational resources to operate on potentially large data sets of information and to interface to advanced sensor technology via current scene projectors. Nallatech Ltd has been focused in the area of low latency hardware and algorithm development for many years. In collaboration with Matra British Aerospace Dynamics UK, minimum latency systems have already been developed offering latency of only several video lines in 3D target scene generation systems. The rapid progression of FPGAs towards 1 million gate devices together with the ever increasing performance of today's DSPs have allowed Nallatech to formulate an architecture that is particularly suited to HWIL systems.

Paper Details

Date Published: 19 July 1999
PDF: 12 pages
Proc. SPIE 3697, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing IV, (19 July 1999); doi: 10.1117/12.352893
Show Author Affiliations
Allan J. Cantle, Nallatech Ltd. (United Kingdom)
Malachy Devlin, Nallatech Ltd. (United Kingdom)
Eric Lord, Matra British Aerospace Dynamics Ltd. (United Kingdom)


Published in SPIE Proceedings Vol. 3697:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing IV
Robert Lee Murrer, Editor(s)

© SPIE. Terms of Use
Back to Top