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Proceedings Paper

EUV mask patterning approaches
Author(s): Pei-yang Yan; Guojing Zhang; Patrick Kofron; Jenn Chow; Alan R. Stivers; Edita Tejnil; Gregory Frank Cardinale; Patrick A. Kearney
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Paper Abstract

In the last two years, we have developed tow Extreme UV (EUV) mask fabrication process flows, namely the substractive metal and the damascene process flows, utilizing silicon wafer process tools. Both types of EUV mask have been tested in a 10X reduction EUV exposure system. Dense lines less than 100 nm in width have been printed using both 0.6 micrometers thick top surface imaging resists and ultra-thin DUV resist. The EUV masks used in EUV lithography development work have been routinely made by using the current wafer process tools. The two EUV mask processes that we have developed both have some advantages and disadvantages. The simpler subtractive metal process is compatible with the current reticle defect repair methodologies. On the other hand, the more complex damascene process facilitates mask cleaning and particle inspection.

Paper Details

Date Published: 25 June 1999
PDF: 5 pages
Proc. SPIE 3676, Emerging Lithographic Technologies III, (25 June 1999); doi: 10.1117/12.351102
Show Author Affiliations
Pei-yang Yan, Intel Corp. (United States)
Guojing Zhang, Intel Corp. (United States)
Patrick Kofron, Intel Corp. (United States)
Jenn Chow, Intel Corp. (United States)
Alan R. Stivers, Intel Corp. (United States)
Edita Tejnil, Intel Corp. (United States)
Gregory Frank Cardinale, Sandia National Labs. (United States)
Patrick A. Kearney, Lawrence Livermore National Lab. (United States)

Published in SPIE Proceedings Vol. 3676:
Emerging Lithographic Technologies III
Yuli Vladimirsky, Editor(s)

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