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Proceedings Paper

Reduction of postdevelop defects and process times for DUV lithography
Author(s): Murthy S. Krishna; Emir Gurer; Ed C. Lee; Gary E. Flores; Sandra S. Ooka; John W. Salois; Royal Cherry; Reese M. Reynolds
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Paper Abstract

As the semiconductor industry moves into deeper sub-quarter micro regime, minimization of post develop process defects is of paramount significance in manufacturing environments. Reduce defects levels can significantly increase the yield in production, resulting in substantial cost savings and also reduce time to market of new devices. Typical approaches to reduce defect levels include extension of the DI rinse time immediately after completion of photoresists development, use of multiple rinse steps and variable rinse spin speed. However, many of these penalize the process throughput. The uniqueness of this project was the use of enhanced rinse hardware with a mechanistic understanding and characterization of defect generation for an advanced DUV resist.

Paper Details

Date Published: 14 June 1999
PDF: 9 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350842
Show Author Affiliations
Murthy S. Krishna, Silicon Valley Group (United States)
Emir Gurer, Silicon Valley Group (United States)
Ed C. Lee, Silicon Valley Group (United States)
Gary E. Flores, Silicon Valley Group (United States)
Sandra S. Ooka, Silicon Valley Group (United States)
John W. Salois, Silicon Valley Group (United States)
Royal Cherry, Silicon Valley Group (United States)
Reese M. Reynolds, Silicon Valley Group (United States)


Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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