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Proceedings Paper

Parameter extraction framework for DUV lithography simulation
Author(s): Nickhil H. Jakatdar; Junwei Bao; Costas J. Spanos; Xinhui Niu; Joseph J. Bendik; Stephen L. Hill
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Paper Abstract

As the semiconductor industry moves into the deep submicron range, the costs associated with wafer processing are increasing rapidly. This calls for improved simulation capabilities that provide information for meaningful 'what if' analysis. This work proposes a common methodology for extracting information from FTIR, dissolution rate monitor and ellipsometry measurements, to be ultimately used for the calibration of commercial lithography simulation tools. Using global optimization techniques, this approach uses cross-section CD data available in fabs to tune the simulation engine, thus giving it the predictive capabilities that could potentially improve yield ramp rates and hence reduce development costs. Results of this framework for a commercial Shipley resist are presented.

Paper Details

Date Published: 14 June 1999
PDF: 10 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350831
Show Author Affiliations
Nickhil H. Jakatdar, Univ. of California/Berkeley (United States)
Junwei Bao, Univ. of California/Berkeley (United States)
Costas J. Spanos, Univ. of California/Berkeley (United States)
Xinhui Niu, Timbre Technology Inc. (United States)
Joseph J. Bendik, National Semiconductor Corp. (United States)
Stephen L. Hill, Bio-Rad Labs. (United States)


Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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