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Proceedings Paper

Effect of the control of global planarity of intermetal dielectric layers on the lithographic process window
Author(s): Shani Keysar; Leah Markowitz; Corin Ben-Gigi; Rama Tweg; Ayelet Margalit-Ilovich; Avishai Kepten; Amir Wachs; Roey Shaviv
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Paper Abstract

The sensitivity of lithographic process window to global planarity of the inter metal dielectric layers is established in this work. The inter metal dielectric layers, between the metal layers, were prepared by utilizing the H2O2/SiH4 chemistry known as the 'Advanced Planarity Layer (APL)'. Four degrees of global planarity were tested within the APL process window, utilizing different H2O2 stabilization pressures. SEM cross sections were used to determine the degree of planarity in the CMOS product and at lithographic test structures. The lithographic process window and the effect of the stepper leveling system were defined for typical high and low topographies. The results how a strong link between the lithographic process window to degree of global planarity of the APL. Good global planarity enlarged depth of focus and energy latitude, allowing a wider lithographic process window. Also, in cases of improved APL planarity, the stepper leveling system had only a limited contribution to a lithographic process window. This control over the global planarity of the inter metal dielectric layers and the wide lithographic process window that results eliminate the need for CMP at 0.5 (mu) technology.

Paper Details

Date Published: 14 June 1999
PDF: 7 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350815
Show Author Affiliations
Shani Keysar, Tower Semiconductors Ltd. (Israel)
Leah Markowitz, Tower Semiconductors Ltd. (Israel)
Corin Ben-Gigi, Tower Semiconductors Ltd. (Israel)
Rama Tweg, Tower Semiconductors Ltd. (Israel)
Ayelet Margalit-Ilovich, Tower Semiconductors Ltd. (Israel)
Avishai Kepten, Tower Semiconductors Ltd. (Israel)
Amir Wachs, Tower Semiconductors Ltd. (Israel)
Roey Shaviv, Tower Semiconductors Ltd. (Israel)


Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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