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Proceedings Paper

New approach to correlating overlay and yield
Author(s): Moshe E. Preil; John S. McCormack
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Paper Abstract

Integrated circuit design rules are defined with a given overlay tolerance, but the exact correlation between measured overlay on product wafers and die yield is notoriously difficult to quantify. Interest in better quantifying this relationship is not merely academic. The ability to shrink the overlay design rule by even a few nanometers would allow more good die to be printed on every product wafer, providing a substantial economic benefit. Conversely, if the actual distribution of overlay errors across a wafer is slightly worse than anticipated in the design rules, the resulting shortfall in yield would be difficult to identify and correct.

Paper Details

Date Published: 14 June 1999
PDF: 9 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350808
Show Author Affiliations
Moshe E. Preil, KLA-Tencor Corp. (United States)
John S. McCormack, KLA-Tencor Corp. (United States)

Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

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