Share Email Print
cover

Proceedings Paper

Alignment and overlay metrology issues for copper/low-K dual-damascene interconnect
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The alignment and overlay metrology issues for various damascene process architectures were studied and optimized. The Buried Hard Mask, Via First and Trench First approaches are studied comparatively for the Via to Metal1 and Metal2 to Via alignments. Alignment capability was studied by the alignment signal strength and alignment repeatability. Overlay metrology capability was studied by the overlay target appearance, static repeatability, target correlation and Tool Induced Shift. Final overlay measurement and long term overlay stability were used as a mean to verify the result. A Design of Experiment was done with splits in the hard mask material/thickness and the degree of copper CMP. It was found that for Metal2 alignment to Via, the Buried Hard Mask approach possess a showstopper unless one align Metal2 to Metal1 instead. The effect of CMP to the alignment to Metal1 level seems to have less trouble than the Tungsten CMP counterpart except the overlay target acquisition might be difficult for underpolish case. The choice of which damascene approach to take depends also on the trade off between overlay and CD control and other process performance and should be customized by individual's requirement.

Paper Details

Date Published: 14 June 1999
PDF: 9 pages
Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); doi: 10.1117/12.350797
Show Author Affiliations
Kafai Lai, SEMATECH (United States)
Chris Nelson, KLA-Tencor, Inc. (United States)
Mark R. Breen, SEMATECH (United States)
Theodore G. Doros, SEMATECH (United States)
Dan W. Holladay, SEMATECH (United States)


Published in SPIE Proceedings Vol. 3677:
Metrology, Inspection, and Process Control for Microlithography XIII
Bhanwar Singh, Editor(s)

© SPIE. Terms of Use
Back to Top