Share Email Print

Proceedings Paper

Spinnable and UV-patternable hybrid sol-gel silica glass for direct semiconductor dielectric layer manufacturing
Author(s): Mark P. Andrews; Ping Zhang; S. Iraj Najafi; Keith K. Chao; Nicholas F. Pasch
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The introduction of the hybrid sol-gel silica glass for direct semiconductor dielectric layer process involves three aspects of photolithography processes. First, the hybrid sol-gel silica glass is possible for the low k dielectric process. Second, it is also photosensitive and UV- patternable at 193 nm or shorter wavelength as the photoresists. Third, it can be used for direct dielectric process that can dramatically simplify the process flow and act as both dielectric materials and photoresist. To directly fabricate semiconductor dielectric layer by using spin-on and UV-patternable materials, to grow glass directly on the quartz, glass or even on the wafer substrate, to have photosensitive materials suitable for direct dielectric layer lithography process is in demand. With decreasing feature sizes, shorter wavelength for exposure is needed. At 193 nm wavelength, most of the materials are not transparent. Hybrid sol-gel silica glass in one of the UV- patternable materials for direct electronic device processing. It may be useful for reticle, DRAM, flat panel or even ASIC manufacturing. It can be 'formed' into intricate and precise 3D configuration. Exposure to DUV or 193 nm light result in a polymerization of the underlying sol-gel glass. the process alters the chemical properties within the bulk of the material as well as at the surface.

Paper Details

Date Published: 11 June 1999
PDF: 11 pages
Proc. SPIE 3678, Advances in Resist Technology and Processing XVI, (11 June 1999); doi: 10.1117/12.350178
Show Author Affiliations
Mark P. Andrews, McGill Univ. (Canada)
Ping Zhang, LSI, Logic (United States)
S. Iraj Najafi, Ecole Polytechnique (Canada)
Keith K. Chao, LSI, Logic (United States)
Nicholas F. Pasch, LSI, Logic (United States)

Published in SPIE Proceedings Vol. 3678:
Advances in Resist Technology and Processing XVI
Will Conley, Editor(s)

© SPIE. Terms of Use
Back to Top