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Proceedings Paper

Reconfigurable parallel processor for noise suppression
Author(s): Michael Cuviello; Philip P. Dang; Paul M. Chau
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Paper Abstract

Digital images corrupted with noise regularly require different filtering techniques to optimally correct the image. Software provides convenience for implementing a variety of different filters, but suffers a speed penalty due to its serial nature of the filter calculations. In converse fashion, implementation using ASIC technology allows for a speed advantage due to parallel processing but at the cost of increased hardware overhead for implementing a variety of filters individually. Advances in Field Programmable Gate Array (FPGA) technology offers a middle ground in which the speed advantages of an ASIC and the reprogrammable aspect of a general purpose conventional CPU or DSP software approach are combined. In this paper, we present an FPGA-based, reconfigurable system, that can perform an assortment of noise filtering algorithms using the same hardware. Implementation of Gaussian and salt-and-pepper noise are evaluated for this system.

Paper Details

Date Published: 24 May 1999
PDF: 9 pages
Proc. SPIE 3663, Medical Imaging 1999: Image Perception and Performance, (24 May 1999); doi: 10.1117/12.349657
Show Author Affiliations
Michael Cuviello, Univ. of California/San Diego (United States)
Philip P. Dang, Univ. of California/San Diego (United States)
Paul M. Chau, Univ. of California/San Diego (United States)

Published in SPIE Proceedings Vol. 3663:
Medical Imaging 1999: Image Perception and Performance
Elizabeth A. Krupinski, Editor(s)

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